Fsk demodulator and modulator combining differentiated counted signals into a weighted analog output

ABSTRACT

A demodulator for frequency-shift modulated telegraph signals using at least two different signal frequencies, comprising means for deriving from the received wave control signals corresponding to the passages through zero of said wave, means for deriving delayed signals from said control signals, a clock pulse generator having a frequency much higher than said frequencies, means for applying said pulses to a binary counter having a plurality of stages, means for resetting said counter to an initial state by said control signals, and logic circuits means including a storage type data-gating circuit controlled by said control signals and displaying the state of said counter in the form of a group of binary signals. The latter are combined into an analog signal which, after being amplified, is applied to a threshold circuit, and the signals appearing at the output of the latter circuit are applied to a utilization terminal. It is shown that a circuit for modulator operation may be obtained by combining most elements of the demodulator with a frequency divider for the pulse frequency and a decoder.

United States Patent 72 Inventors Maurice A. Manlere; 3,466,550 9/1969Wolfet al. 325 320 Jacques K. Meile, both of Paris, France 3,474,341 10/1969 Crafts et a1. 178/66 [21] Appl. No. 27,711 3,512,087 5/1970 Lewis325/320 [22] Filed Apr. 13, 1970 3,543,172 11/1970 Seppeler 178/66 [45]Patented Aug. 17, 1971 Prim y ExammerRobert L. Griffin 73] Assignee kiiils p'tz fiz p Telephomques Assistant Examiner-James A. Brodsky 32Priority Sept. 22, 1969, Dec. 18, 1969, Jan. 31, Abraham 1970 w I [33]France ABSTRACT A d emodulator for frequency-shift modulated [31] 321504389981! 03264 telegraph signals using at least two different signalfrequencies, comprising means for deriving from the received wave [54]FSK DEMQDULATOR AND MODULATOR control signals corresponding to thepassages through zero of COMBINING DIFFERENTIATED COUNTED said wave,means for deriving delayed signals from said con- SIGNALS INTO AWEIGHTED ANALOG OUTPUT trol signals, a clock pulse generator having afrequ ency much 9 Chums 10 Drawing Figs 1 higher than said frequencies,means for applying said pulses to v a binary counter having a pluralityof stages, means for [52] US. Cl U 325/18, resetting said counter to aninitial state by said Control Signals 325/163, 325/320, 178/60, 178/88,32 /12 and logic circuits means including a storage type data-gating332/9 circuit controlled by said control signals and displaying the [51] Int. Cl H04!) l/40, State f said counter in the f of a group ofbinary Signals "04127/14 The latter are combined into an analog signalwhich, after [50] Field ofSearch 325/18,2l, being lifi d is applied to athreshold circuit and tha 30, 163, 320; 178/66, 88; 329/104, 126, 1.2;332/9 signals appearing at the output of the latter circuit are applied56 R f cued to a utilization terminal. It is shown that a circuit formodulal e I tor operation may be obtained by combining most elements ofUNITED STATES PATENTS the demodulator with a frequency divider for thepulse 3,412,205 1 H1968 Saeger 17 8/88 frequency and adecoder.

111 117 DIGITAL T0 ANALOG CONV. AMPL HLTER THRESHOLDI-Q i 04 115 cm 1 221.1 22 1 122 225, v AMPLIFIER I MEMORY TRANSFER CCT 414 3 t T DECODER501 502/ 503/ 504/ 250 1 I I I I I 250 I z 1 i i I, -siAeE couinER T m{6- STAGE 1 COUNTER I i I I 1.01. r.- l I l i i 1 L 4135 321/ 422 324 22402 1.03 323' 1.12;| FY23 Lo OPERATION MODE SELECTION SWITCHING CIRCUIT300 a 1.21. 3OI i. 303 304/ 305/ 306 5 \312 L 65 313 1 DIFFER DELAY H .4I CLOCK H CCT *7 CCT 2i? 2'11. 245 2is R PATENIEU AUG! 7197i 3600 660sum 1 UF 6 v Fig.1

THRESHOLD CCT and T AMP. V

m/ M m PATENIED mm 1 l97l sum 3 or 6 Fig 5 F SK, DEMODULATOR ANDMODULATOR COMBINING DllFFERENTIATED-COUNTED SIGNALS INTO A WEIGHTEDANALOG OUTPUT tors, for telegraphic or similar signals.Modulatorsthusdevisedr therefore from a second subject matter oftheinventionz Also, the demoduiatlngiand modulating:devices-according tothe invention are, by the natureofthe counting-and'logic circuitswhichthey use, capable,- oft'being produced; in simpleandv low-cost forms,for instance,, by integrated; circuit" technique.

The: invention,v has particular. advantages, in' cases in which;frequency filteringin a relatively narrow pass bandis required; forthe-transmission channel, to limitthe;occupiedfrequency band width,vandto facilitate, multiplexingwith'other channels; A. case, ofthiskind'isfound inter alia inifrequency shift-har monic. telegraphy(voice-frequency telegraphy). where; a: number of telegraph,channelseach uscva fraction of-aifrequemcy band whosetotalwidth isequal to the width" of one: telephonechannel.

It will be assumed byway ofexample insuch-acase thatthe" telegraphicsignal-is a two-state signallwhosev twostates-arerespectively,represented by nominal frequenciest f1 and fAfterfilt'ering, the transmitted sinusoidal ,wave. reaches the instantaneous frequency; f, orf only-aftera ttirnewwhich is too: long forconventional, frequency demodulation: methods. to yield demodulated(detected) signals whose: between-states changeover" times are,accurately determined; and little af= fected by interferenceand noise.Toobviate this disadvantage, therefore, the invention determinessuch-changeover timesby meansof a direct method in which such times aredetermined" by the passageof the.--instantaneoustfrequency of thereceived; wave through a particular value,.for instance, the arithmeticimean fl,=(f,+f )/2,of the nominal frequencies J} and f Intheventionmakes it unnecessaryior'the receivedwave .torernainz.

at thecorrespondingmominal frequency for: any appreciable:

' length of'time so thatthe state at aparticular *tir'neuof the;modulatingtelegraphic signalcanbe identified,-,thefilteringof suchwaveat transmission and at receptionneednotabelvery stringent andcanbeperformed by-means of simplecheap'filterss Frequency measuring systemsareknown, for-instance; from- Frenchtspecification 1,5 1 1,605,whichzoperate on:the:.basis of a p stage ,-binary counter counting;during, a, half-period: or a whole period of the -,received, wave, thenumber of pulses-1 deliveredby a clock pulsegeneratoratarepetitionwfrequency-- w-hichis much higher than the frequency toberneasured. As a ruleinsuch systems, only the oreach'digittof'greatestweight of-the group of pbinary digits. displayedby thecounter is used,Adisadvantage,inthiscase is ,thattif the result of the, counter-isnear-(2"-l) or 2?,any slight,interferenccito-the receivedwave, for instance,due =to-noise, may cause a sudden changein the value of thedigit;oflgreatestvweight of the p-digit' group,

with the result of a large error in frequency measurement (or in thedetection of coincidence of such frequency with a predetermined value),the error possibly affecting the detected signal. Appropriate frequencyfiltering of the detected signal can remove random variations due tointerference of this kind, but to be satisfactory any such filteringneeds relatively complicated and costly multisection'filters.

Inthe system" according to the invention, on the other hand, thedetected signal can be filtered just by a very simple lowpassfilter,since the disadvantage just outlined is obviated by conversion of all pdigits of'the group of binary digits into a single analog signal whosevalue can be impaired very little by such interference. Identity betweenthe measured frequency I value and a predetermined value is checked by athreshold circuitiwhich indicates the time at which the magnitude of thelatter signal passes'throughsuch predetermined value.

The: general assumption will be made in the description to begivenhereinafter that the'modulating signals are two-state signalsrepresented by two predetermined nominal frequencieszff, f5, foralthough the use of the invention is not limited just to two-statesignals, use with two-state signals is the most importantpractical one:

Thisinventiomprovides a demodulator for frequency-modu- H lated:telegraph signals having at least two different signal statesrepresented by a different respective predetermined nominal-frequency ofa substantially sinusoidal received wave, the'saiddemodulatorcomprising:

an input receiving. the wave in the form of a substantially sinusoidalvoltagewhosefrequency mayvvary in time;

meanstforderivingfrom'such wave, by time'differentiation atselected'instants when such voltage passes through zero, a control'signalcorresponding to each such selected instant;

means for deriving a delayed signal from the said control n a clockpulse generator delivering a sequence of clock pulses at a: repetitionfrequencyF much higher than any of the saidnominal. frequencies; meansforapplying suchsequence to the counting input of a p -stagezsbinarycounter, p denotingan integer, the said counter displaying 'the modulo2? residue of .the number of clock pulsesapplied thereto when the numberexceeds 2;

means for controlling resetting of the counter to a predeterminedinitial stateby the delayed signal, and

logic. circuit means comprising a storage type data-gating circuitcontrolledby the said control signal and which displays the'state of thecounter in the form of at leasta portion of a groupof'p'binary signalsapplied to p display terminals respectively;

thevsaid demodulator being characterized by:

meansforcornbining at-least some of the group of p binary signals toform an analog signal formed by a voltage'varyin g in dependence uponthe makeup of such group;

meansfor applying the said analogesignal to the input of a thresholdcircuit formed by cascading a low-pass filter, at least onevlinearamplifierand a decision'circuithaving at least one threshold'level, and

means for applying to autilization terminal the output signal ofsaiddecision'circuit;

Preferably, the chosen passages through zero are the passages of thesubstantially sinusoidal-voltage through zero in a predetermineddirection;

ln themost'widely used-formof the demodulator according totheinv'ention; the number of the predetermined frequencies istwo;the=lower frequency hereinafter being called f and the higherfrequency hereinafter being'calledfl.

- in aipreferredtform'of the'demodulator according to theinvention-,=the portion of the groupof p binary signals comprises the'digits oflgre'atest weight in the binary number counted by the counter.5:1

in alpreferred formof the demodulator according to the invention,theinitial state ischosenin accordance with rules tobecdefined-rhereinafter'withthe aim of ensuring therequired accuracy\in: determining .the instantaneous frequency of the demodulated'signal.

The invention also provides a frequency-modulating device using, likethe demodulator, a clock pulse generator and a multistage binarycounter. Clock pulses of frequency F are applied to the counting inputof the binary counter, a number of stages of which are coupled with acorresponding number of inputs of a decoder, operating of the latterbeing dependent upon a preadjustment governed by the choice of the clockfrequency F and of the telegraph frequencies f,, f,, and upon theinstantaneous value of a modulating signal applied to an input. Themodulator serves to produce the frequencies f,, f from the frequency Fby division thereof by an integer whose value depends upon the state ofthe decoder, this integer or factor varying in accordance with theinstantaneous value of the modulating signal. Clearly, therefore, themodulator just described uses many of the same elements as thedemodulator, so that it becomes possible to build a device adapted tooperate selectively as a demodulator or as a modulator, through theagency of relatively simple selective switching means acting on thecommon items. Preferably in this case, the binary counter comprises twopartial cascaded counters whose association with one another and withthe other items can be varied by switching elements for demodulator ormodulator operation. As already stated, the frequencies of the modulatedsignals are produced by division of the clock pulse repetition frequencyF, the division being performed by the partial counters in cooperationwith the decoder.

The invention will be more clearly understood from the followingdetailed description, reference being made to the accompanying drawings,in which:

FIG. 1 is a schematic diagram of a demodulating device according to theinvention;

FIG. 2 comprises two graphs 2a and 2b to explain the operation of thedevice shown in F IG. 1;

FIGS. 35 show alternative forms of parts of the device shown in FIGS. 1and 2;

FIGS. 6 and 7 help to show an operating feature of the same device;

FIG. 8 is a schematic diagram of a preferred embodiment of thedemodulator or detector according to the invention;

FIG. 9, with its seven graphs 9a to 93, helps to show the operation ofthe embodiment shown in FIG. 8, and

FIG. 10 shows an embodiment of the device according to the inventionwhich can be selectively used as either a demodulator or a modulator.

Referring first to FIG. 1, showing a schematic diagram of a demodulatoraccording to the invention, a substantially sinusoidal received wave isapplied to the input 1 of a time differentiation circuit 2 whichdelivers a very brief control pulse at its output 3 whenever the ACsignal applied to input 1 passes through zero. Prefers ly, the controlpulse is produced only when such voltage passes through zero in oneparticular direction, so that two consecutive pulses of this kind areseparated by an interval equal to the period of the voltage applied toinput 1.

A conventional delay circuit 65 has applied to its input the voltagefrom output 3 of circuit 2 and transmits the latter voltage with a veryslight delay to the zero-resetting input 60 of a binary counter 70having four stages 6l-64and a counting input 6, the latter being drivenby the output of a generator 4 supplying clock pulses having arepetition frequency F. The number p has therefore been taken to be 4 inthe example shown in FIG. 3..

Each stage of counter 70 can take up two states conventionally calledone" and zero" and comprises an output S, at which a voltage appears;such voltage is, for instance, positive when the stage is in the1"state, whereas when the same voltage appears at a second output of thesame stage, the same will be said to be in the zero state. The twooutputs of each stage are connected to an equal number of differentinputs of a logic circuit 100 which also has an actuating or controlinput energized via connection 30 from output 3.

Circuit 100 comprises four elementary data-gating circuits (71, 81, 91),(72, 82, 92), (73, 83, 93), (74, 84, 94), each comprising two AND gatesfor instance, 71 and 81, each having one input connected by connection30 to output3 and the other input connected to output 8, ofa'correjsponding one of the stages 6164. Each pair of gates, forinstance, the pair 71, 81, drives a bistable circuit, for instance, 91.The circuit arrangement forms a storage type data-gating circuit havingfour outputs 101104 connected to the bistable circuit 91 94,respectively. Gating is controlled by any control pulse delivered atoutput 3, each such pulse bringing the outputs 101104 respectively intothe same state as the output S, of the corresponding stage 61-64respectively; alternatively, if the outputs 10l104 are already in thesame state as the corresponding outputs S,, the control pulse deliveredat output 3 does not cause any change in the state of the outputs 201-104. By way of the delay circuit 65, any control pulse resets thecounter to a predetermined initial state which can be the zero state orany other desired state; this resetting occurs after data gating hasbeen effected as far as outputs 10l-104.

Circuit arrangement is a digital-to-analog converter showndiagrammatically as a group of four resistances R1, R2, R3, R4, whichare of different and appropriately weighted values and which each haveone end connected to one of the outputs 101l04 respectively, the otherends being connected to a common output 111 connected to the input of alinear current amplifier 112 delivering at its output 113 a voltage V(relatively to a reference potential, for instance, ground potential)proportional to the current I which is the sum of the currents i,, ii,,; i, flowing through the respective resistances R1, R2, R3, R4.Output 113 is connected to the input of a low-pass filter 1 14 whoseoutput 1 15 is connected to the input of a circuit 116 having an output117. Circuit 116 comprises a high-gain amplifier followed by a thresholddetector which can have one or more threshold levels. If V,, and V,,,denote the potentials at the outputs 115 and 117 (relatively to thereference potential), V,,, remains zero or very small if V, is below athreshold V, (if there is only one threshold), the information whichV,,, represents in this case having, for instance, the binary value 0.If V reaches and exceeds the threshold V the output stage of the circuitarrangement 116 is saturated due to the high gain thereof and V,,, thenassumes a value V, which is appreciably different from zero and whichconventionally represents the one" value of V,,,. The analog informationformed by the potential appearing at output 111 is therefore convertedinto a binary numerical data item V,,, which appears at output 117 andwhich has the zero value or the one value according as the potentialappearing at output 1 11 is below or above a predetermined threshold ofV,,. FIG. 2, containing two graphs 2a, 2b, will help to show how thejust described device operates. Graph 2a is related to two axes-timealong the abscissa and instantaneous frequency along the ordinate. Abroken line 40 represents the binary value of the modulating signal,with the value 0 representeu by a signal of frequency f during the timeintervals from t, to t, and from 1;, to t while the value I isrepresented by a signal of frequency f, during the time intervals fromt, to t,, and from t, to i,,. In practice, due to the filtering offrequency-modulated signals, the actual curve representing instantaneousfrequency has a shape something like the solid-line graph 41, as if thefrequency were varying continuously between a value near f, and someother value near f,. The variation in instantaneous frequency isrelatively slow in some parts of the curve, such as the parts 4244, butis much faster in parts such as 45, 46

corresponding to changes in signal state from one frequency to theother. The graph 41 therefore shows the pattern of variation of theinstantaneous frequency of the signal. Of

course, if more than two frequencies were used the graph 41 would haveone or more intermediate steps between its extreme values.

- Referring now to graph 2b, which is to the same time scale as graph2a, time is plotted along the abscissa but the states j of the counterof the facility of FIG. 1 are plotted in decimal numbering along theordinate; the numbers j also represent, on an arbitrary butpredetermined scale, the decimal value of the voltage V 'proportlonal tothe current I delivered by the converter li.e., to the whole number j.The voltageV at output 115 of filter 1-14 is also shown in graph 2b; thescale is not marked but'is so devised that two pointsrepresentingcorresponding values V and V, have equal ordinates in thefigure.

The values which the counter 70 displays consecutively in time and whichare assumed by the voltage V are indicated by horizontal marks from 0 toat some ofthe whole-number .levels j; the length of each such horizontalline is a proportional representation of the time for which such a givenlevel is maintained. The corresponding consecutive durations succeed oneanother in time without interruption and without overlapping. Any twoconsecutiveihorizontal lines are at different levels spaced apart by oneor more units; variations of one unit or two units of the level j areshown in the drawing by way of example. If modulation rates are high,some spacings may be greater than one unit and only some levels mayappear, inter alia in the parts where frequency variation is fastest;the time intervals denoted by T1, T3, T5, T7 are the time intervalswhere frequency variation is slow, and the time intervals T2, T6, T6, T8are the time intervals in which frequency variation is fast.

In the frequency demodulator shown in FIG. 1, the voltage V,, isproduced by the voltage V,, being filtered in the low-pass filter 1 14.The corresponding pattern of the voltage V is represented in graph 2b bya solid-line curve 47, which shows a flattened variation of the levelsas-compared with the discon tinuous representation provided by thehorizontal lines. Curve 47 has portions in which frequency variation isslow, which have reference arrows d851 and which correspond to the timeintervals T1, T3, T5, T7; variation is much more rapid in theintermediate intervals T2, T4, T6, T8. The threshold voltage V,hereinbefore defined is shown on the graph; a chaindo'tted line 52extending at threshold level intersects curve-47 atpoints 53-56 whoserespective abscissa points are t6, t7, t8 v, r a.

Random rapid changes in the level are not shown on graph 2b and at thescale thereof, but graph 2!; does show that those of such rapid changeswhich may impair detection of the passage through the threshold V,concern those steps of j which are near the threshold-Le, the steps oneither side of the points 5356; clearly, the threshold random variationzone is greatly reduced when the variation of the potential appearing atI l E (or 113) (FIG. 1) has 'alarge number of steps.

In the facility of FIG. 1- the number of steps is defined by the gatingcircuit 1%, controlled via the four stages of counter 70; in some cases,for instance, if the counter has a fairly large number of stages, onlysome of the counter stages need to be usedactually, those of greatestweight-to, provide an adequate reduction of such random variations, thesame being still further reduced by filter R14.

Referring now to H015. 3, which show various embodiments of the low-passfilter of Flt}. 2, filter 138 in FIG. 3' comprises anv RC network,filter M9- Fl'G'. i is an active filter comprising an amplifier 1-21with a negative feedbackcircuit including two impedances 3122, 132 ofappropriatedesign and value, and filter 120 of 5 is the filter preferredfor the purposes of the invention and comprises a capacitor 123 andaresistance 124 and, in series with resistance 124, an amplifier 1'25comprising a negative feedback circuit having-a capacitor 126and-resistances 127', E28. Filters of this kind; andmethodsofcalculating their elements, are well known in the art.-

For. satisfactory operation of the arrangement shown in FIG. 1, thevarious elements which form it are devised to complywith.the followingconditions, which will become clearly apparent from-a study'of graph 2b:

a; Themean level between the top-level regions. as-49 and- 51 and thebottomvlevel regions, as 48-and50; must be substantially equal tothethresholdV,; v

b. The mean level must correspond to a value of the voltage V',, suchthat the numberj representing-such'value in the scale ofnumbers fromOto(2) must be near the mean value--i.e., 7 or B in the caseshown in-thedrawing-or?" or(2"- I) if the binary counter of the facility has ,9stages, and

c. The levels (49,51) and (48,50) must be placed near the centralpointsof the intervals 2",2") and (0, 2") respectively, in whicheventthe difference between these levels is approximately 2".

Conditions (a) and (b) arise of course from the fact that the value )2,of the instantaneous value of the received wave is selected near themean of the extreme values (i.e. f and f which this instantaneousfrequency may take up. A practical reason for condition (a) is that theinstantaneous frequency of the received wave may occasionally haveovershoots such that it may become less than f or greater than f2, andso some safety'rnargin must be retained between those values of thelevelj-(FIG. 1, graph 2b) representing f and f respectively and theextreme values 0 and 2 of the same level, so that the threshold value Vcorresponding to f, is in a substantially linear part of the curvegiving V (or V in dependence upon the instantaneous frequency.

An explanation will now be given, with reference to a nu-' mericalexample, of how to select the values of p and F and the initial state ofthe counter 70 of FIG. 1 for optimum operation of the facility showntherein as regards transmission speed, but without any need for theclock pulse repetition frequency F to be very high.

Using the same references f f; for the nominal frequencies, f, for theirarithmetic mean and T for the duration of the transient conditionbetween twomodulating signals representing different signal states(duration T being the same, for instance, as the duration T of graph 2bof FIG. 2), the instantaneous frequency is obtained by measuring thetime between two passages of the received wave through zero in the samedirection by means of modulo 2" counting of the number of clock pulsesof frequency F occurringbetween such two passages through zero. If it isassumed that the instantaneous frequency varies substantially linearlyduring the time T, a number (Tf of different consecutive instantaneousfrequencies expressed by different numbers j will appear substantiallyduring the period T. The minimum and maximum measurable frequencies fand f are given by:

a denoting an integer and r denoting the initial counting state of thecounter. The measured values lie between these extreme values in such away that:

,so asto retain a safety margin" of 2"I4F between the durations of thetimes corresponding on the one hand to f and f and on the other hand toj} and to f,,,,,, (condition (c) previously referred to). The number ofdiscrete values of the instantaneous frequency which are measurablebetween f and ji -Leg for any two of which the counted numbers of clockpulses of repetition frequency F differ by at least one unit-is ofcourse:

/fi /fz= For accurate measurement, n must be at least equal to thenumber (Tf already found in the foregoing, so that:

2911 or, else P 5* 5201) Turning now to the following numericalexamples:

Telegraphy at 50 bauds T=l 2 ms.; Telegraphy at 100 bauds: T=6 ms.;Telegraphy at 200 bauds T=3 ms'.;

' 5,:15 Hz. for 200 bauds (f f,=240 l-iz.),

Z the condition given in theforegoing for p checks out in all cases inwhich p is at least equal to 5. v A description will now be given of howto choose the clock ffrequencyf. Combining equations (3) and (4), weobtain:

If for a transmission speed R of 40 bauds f], is taken as 1740 Hz. and(f f,) is taken as 60 Hz., equation (6) gives for q the whole number 14for i=0, in which event On the other hand, in the other two casesconsidered in the foregoing where fl,=l680 Hz. with a rate of 100 bauds(f f,=l20 Hz.), and where 1151560 Hz. with a rate of 200 bauds (f,-f=240 Hz.), no whole number is found for q when r=; the countingremainders are not equal to one-fourth of 2" and three-fourths of 2" forf and f, respectively, when r is zero. To make the modulo 2" countingremainders respectively equal to (PM) and (3/4 2") for the frequencies fand f the initial state of the counter is arranged to be not zero but anumber r making the quantity q a whole number; this can be done if r ischosen to have an appropriate value less than 2".

The following table summarizes the numerical results in the case of thenominal frequencies f f and the transmission speeds R hereinbeforeconsidered: n

r (decimal r (binary (p was taken as 5 for all the cases considered inthe table). It is found, for the three considered values of R and f thatthe corresponding values of F must be 807 120, 375 840 and 161 2801-12.respectively. if p were taken as 6, the values for F would be twice thevalues just given.

In a device of the kind shown in FIG. 1, counter operation must not beupset by a data-gating control pulse; for instance, if such a pulse isspaced apart from the immediately preceding counting pulse by aninadequate time interval, the gating control pulse may act before thecounting pulse preceding such gating pulse has had time to change overall the counter stages. This risk must be precluded; the counting erroris one unit if the disturbance affects only the stage of lowest weight,but if the disturbance affects other stages, more particularly thestages of highest weight, the error may be very large.

FIGS. 6 and 7 give a clear explanation for these error risks. Curve inFIG. 6 represents a period of the signal-forming wave plotted againsttime, points 16 and 17 on the time axis each denoting the end of any oneperiod and the start of the next; counting pulses 18 are plotted alongan equivalent time axis below. In FIG. 7, that portion of the curvewhich is immediately adjacent the point 17 on both sides thereof isshown to an enlarged scale; also visible are two consecutive countingpulses 19, 20 which are separated from one another by a time intervall/F. At the time denoted by point 17, a pulse 21 is fonned with effectfrom the passage of curve 15 through zero (in the sense of a decrease inthis particular example); after the pulse 19 has contributed to thecount, the pulse 21 initiates data gating. The counter operates for atime interval T after the passage of a counting pulse. To completelypreclude any risk of a miscount, the time interval between pulse 21 andthe counting pulse 19 must be appreciably larger than T,,; failing this,means can be provided to delay the action of the gating pulse 21adequately, for instance, by using a series delay circuit in connectionwhich connects output 3 to the datagating circuit arrangement 100.

FIG. 8 is a block schematic diagram of a preferred form of a deviceaccording to the invention, in which the gating control pulse id delayeduntil halfway through the interval between the two counting pulses l9and 20, so that the gating control pulse occurs at a position such as 22(shown in broken lines in FIG. 7)i.e., with a time stagger of l/2Frelatively to the final counting pulse. This example relates moreparticularly to the use h ereinbefore referred to on 50-baud Itelegraphy with nominal frequencies of 1710 and 1770 Hz., the countingpulse frequency being 807 120 Hz. and the corresponding period beingapproximately 1240 nanoseconds. In a prior art method used in the devicealready described and in that shown in FIG. 8 and which will bedescribed hereinafter, the counter writein-time is approximately 2030nanoseconds per stagei.e., a maximum of 150 nanoseconds for a S-stagecounter. In this case the pulse 22 is about 600 nanoseconds away fromthe pulse 19 and there is no risk of a miscount.

The arrangement shown in FIG. 8 comprises the differentiation circuit 2having an output 3, a delay circuit 66 and a binary counter 70 having astepping-on input 6 and a zeroresetting input 60. The storage typedata-gating circuit arrangement 100 is connected to the counter stagesby connections (broken lines); connections (broken lines) connectcircuit arrangement to the digital-to-analog converter which has anoutput 111; that part of the circuit which comes after output 111 isdevised in accordance with FIG. 1 and is not shown in FIG. 8. Twocircuits 1 l, 12 are connected in series between the main input 1 andthe input of circuit 2; circuit 11 restores the shape of the signalapplied to input 1 by clipping, and circuit 12 is a coincidence andstorage logic circuit which samples the signal applied to its input 13by means of a periodic signal applied to another input 14. Thelast-mentioned signal is formed in a circuit 23 from oscillationsproduced by a generator 24 at a frequency 2F; circuit 23 has means fordividing the frequency F by 2 at its two outputs 5 and 25, the signalsthereat being in phase opposition to one another; output 5 is connectedto counter input 6 and output 25 is connected to terminal 14.

The graphs of FIG. 9 explain the operation of the arrangement shown inFIG. 8 and refer to the actual case previously mentioned ofvoice-frequency telegraphy, the time intervals under consideration beingas follows:

period of waves near central frequency and characteristic frequencies:about 600 microseconds period and 300 microseconds half-period;

period of frequency F: approximately I240 nanoseconds, and

period of frequency 2F: approximately 620 nanoseconds.

Graph 9a shows the output of oscillator 24 in the form of 620nanosecond-period rectangular signals, and graphs 9!; and 9c show therectangular signals delivered by circuit 23 at outputs 5 and 25respectively, the period of the signals at both the outputs 5 and 25being 1240 nanoseconds and the signals being in phase opposition. Thechanges in level of the signals are marked by a dot below the place oflevel change and correspond to the starts of the respective periods;these changes or transitions form the counting pulse in the case ofgraph 9b and the sampling pulse in the case of graph 90.

Graph 9d shows the signal delivered by circuit 11 from the signalapplied at input 1 during the half-period terminating at a time as 17 inFIG. 6; the line representing the signal delivered by circuit 11 is abroken line, just as in the other graphs, because of the duration of thehalf-period which is very long in relation to 620 nanoseconds.

Graph 9e represents the signal delivered by circuit 12; at itstransition ca (output 14, FIG. 8 and graph 90) the signal of graph 9d(terminal 13, FIG. 8) is at its high level (dh); the signal in graph 9cis changing from its low value to its high value (ch) but this levelchange has no effect on the differentiation circuit 2; at the nexttransitions of the signal in graph 90 from (cb) to (cm) the signal 9d isat its high level and is not affected by the latter transitions; at 17the signal in graph 9d is dropping to its low level (at the time markingthe end of the period); the next transition (cn) (change from low levelto high level) coincides with the low level of the signal in graph 9dand this coincidence changes over the signal in the graph 9e from itshigh level (eh) to its low level. After this transition the circuit 2produces a pulse (reference ft in graph 9)) and outputs such pulse atits output 3; the pulse ft then triggers data gating. After the pulseft, delay circuit 66 applies to the zero-resetting input 60 (FIG. 8) aslightly delayed pulse 2. t. gz (graph 93) which resets the counter tozero after the states of the various counter stages have been gated tothe outputs of the circuit arrangement 100; the latter outputs store thecorresponding data until the next control pulse.

The delay tz of the delay circuit 66 is so chosen that the sum of suchdelay plus the zero-resetting time of counter 70 (time from theapplication of a. pulse to the zero-resetting input 60) exceeds theminimum holding time for the AND gates of the circuit arrangement 100which is necessary for satisfactory operationof the bistable elementsofcircuitarrangenient 1'00.

The delay of circuit 66 can be a few tens of nanoseconds; in-' tegratedcircuit technology may make the delay circuit 66 unnecessary since thezero-resetting time may on its own exceed raphy or data transmissionanda demodulatorv for the same kind of signal. Both thedemodulator"andsthernodulatortherefore use largely the same. workingunits, butconnected .up differently through the. agency of I anappropriate selective switching circuit. A system of this kindisofcourseeconomically advantageous, enabling as it does thesameworking units tobe used'to construct facilities for. which different elements havepreviously been required and thus enabling thenurnber of different kindsof element used ina given total number of communication circuits to bereduced.

Returning to the three examples given in the foregoing of telegraphy attransmissionspeedsR of50, 1.00 and 200 bauds forany value of p; andwithnormal-transmitted' frequenciesfl, of 1710 and. 1770, i620 and i740,l440-and i680 l-l'z'.,

respectively, the quotients Q Q iarisingffrom division of'the'clock'pulse repetition frequency F by the frequencies f} and f,

Theformulas just given show that signals of frequencies f and;ficanalways be obtained from clock pulses of'frequency F-by relativelysimple frequency division. operations. which are purely prior art.

lf'p isnow taken as 6, then HQ andQ will-befound in each case to betwice-what they were when p wasSg-so that for are respectively for thecasesjust set forth:

r=0;.;==32 and r=l6; The. block-schematic, diagram of FIG. l0 shows howamodulator and a demodulator canbe devised atchoice in the.

. Correlatively, theinitialstate. vaiues required for theacounter when pis 6, characterized by the nurnber r hereabove defined,v

three cases just described-although without. limitationjust to these.three caseson thebasis of the same worki'ngunits, togetherwiththeoscillators at the fretnzenciesf andf which are required for;operation-of the moduiator, by different interconnections between theunits and by. the use of a small number of extra elements. In FIG. 10,where elements which are the same as in FIG. 1 have the same references,there can be seen: the input 1 for the wave to be detected; the timedifferentiating circuit 2 which prepares control pulses from thepassagesof such wave through zero; the delay circuit 65 which receivesthe control pulses and delivers delayed control pulses; the clock pulsegenerator 4; thestorage type gating circuit and the digita l-to:aglogconverter 110 with its output 117 where the detected signal'isreceived. In FIG. 10 the fourstage counter of FIG. 1 is replaced by asix-stage counter formed'by cascading two partial binary counters 250,260having four and six stages respectively, only some of the stagesbeing used for demodulator operation. For demodulator operation too,counter 2501s followed by counter 260 in the cascade, whereas theorder'is reversed for modulator operation. The interconnectionchangesjust referred to and other interconnection changes are theresponsibility of a main operation selector circuit 300 whose operationis controlled by ordinary e.g. manual two-way switches 211, 213216, aswill be described hereinafter.

Also visible in FIG. 10 are the following extra elements which areabsent from FIG. 1 and which are not required for demodulator operationbut are necessary for modulator operation. These extra elements are:input 217 for the modulating, signals; a decoding: circuit 264 which incooperation with thecounters 250, 260 divides the clock pulse frequencyF by a factor Q, or Q which is other than a power of 2 and which can bee.g. 57 or 59,27 or 29 or 12 or 14, so that after a second'division by16 of' the result of the first division, the fi-equenciesf and f areproduced from the frequency F by the procedure hereinbefore described;andan amplifier 240 and an output 241 for frequency-shift-modulatedsignals.

. For demodulator operation the circuit arrangement shown inFIG. 10operates as-follows:

The-wave to be detected is received'as a voltage at the timedifferentiation circuit input 1; the time difi'erentiation circuit 2delivers control pulses corresponding to at least'part of the passagesof such voltage through zero. The selector 214 is placed'in itsleft-handposition so that, through the agency of relays in circuit 300', a directlinkis made between connection 30-! and connection 401 (serving the samepurpose as 30 in FIG. 1) extending'from circuit '300 towards the controlinput of circuit (as in FIG. 1). A direct link is also made betweenconnection302 and connection 402 which extends from circuit 300 tozero-resetting input 460 which serves the same'purpose for'thefour-stage counter 250 as does the circuit 60"for the counter 70in FIG.l-i.e., enabling the counter 25010 be reset to a predetermined initialstate by delayed control pulses coming from 65. When placed in itsleft-hand positionin the drawing,switch 211 allows the pulses fromcircuit arrangement 2 to pass to the selective switching circuit 300.Delayed. control pulses are delivered-by delay circuit 65 via connection302 to circuit 300. When'in the left-hand (detection) position, theswitches 213, 2l4-earth the connections 303,- 304 associated withcircuit '300.When in their right-hand position, switch 213 linksconnection 303 to the modulating signalinput 217 and switch 214 linksconnection 304 to the positiveside of a DC source 218 whose negativeside is grounded. Changingthepotential of the connection 304 acts, bywayof electromechanical-or electronic relays in circuit 300, to producedifferent interconnections between the various connections extending tothe circuit 300; according as demodulator or modulator operation hasbeen selected.

By usingthree out of four possible paired combinations oftheir'positions; the two-way switches 215, 216 enable each ofthe-connections 305'and 306 to the circuit 300"to be brought toloneorthe other of two different potentials (ground potential or. the positivepotential of DC source 218), with the resultgithrough the agency ofrelays in circuit 300,'that the connections of the counters 250 and260"are arranged for one or other of the three'types of telegraphoperation referred to (50, 100, and'200 bauds) andtheinitialstate of thecounters is made appropriate for the particular case concerned.Simultaneously, clock pulse generator 4 is set to the appropriatefrequency F via the connection 313.

For demodulation, when the switches 213 and 214 are in their left handposition, a direct link is made in the circuit 300 between theconnection 312 from the clock pulse generator 4 and the connection 412extending to the counting input of counter 250, and another direct linkis made in circuit 300 between the counting output connection 403 ofcounter 250 and the counting input 404 of counter 260. Fixed connections501-505 connect the second, third and fourth stages of counter 250 andthe first and second stages, respectively, of the counter 260 to fiveinputs of the gating circuit 100 which have five outputs 221-225connected to five corresponding inputs of the digital-to-analogconverter 110 (serving the same purpose as the element 110 in FlG. 1),the latter connection being direct in the case of outputs 221, 222, 224,225 and by way of a link in circuit 300 between connections 411 and 413in the case of output 223. Converter output 111 is connected to theinput ofthe system 112, 114, 116 (as in the case in FIG. 1) and thedemodulated signals are received at output 17.

Consequently, when the system operates as a detector in the manner justdescribed, six counting stages are used which comprise all the countingstages of counter 250 plus the first two stages of counter 260(corresponding to the case of p=6), whereas in the gating circuit 100and converter 110 the signals delivered by the first stage of counter250 are not used; since the last-mentioned stage is the stage of leastweight, the required accuracy can be obtained by using the five otherstages of the assembly 250, 26%.

The connection pairs (322, 322) and (323, 324) associated with the firsttwo stages of the counter 260 each have one or the other of theirelements connected inside circuit 300 to the connection 402 conveyingthe delayed pulses from the delay circuit 65, according to the selectedtransmission rate, by means of the switches 2E5, 216, so that thedelayed pulses from the delay circuit 65 can bring the first two stagesof the counter 260 to the appropriate initial state which depends uponthe value of the number r which, as already explained, may be or 32 or l6. The initial state which the delayed pulses coming over the line $02to the point E60 impart to the four stages of the counter 250 aiways thezero state. In demodulator operation the last four stages of counter 260are zero reset via a connection made in circuit 300 between line 302 forthe delayed pulses from deiay circuit 65 and the common line 422extending tron: circuit 300 to the iast four stages of counter 260.Through the agency of the decoder 264, the last-mentioned countersensure that the connections between the lines 301 and 4M and between 302and 402 or 302 and 422 are made only once a particular counting state(14 for 50 bauds, 7 for 100 bauds and 3 for 200 bands) has been reached.A description will now given how the elements shown in FIG. 10 arearranged for mo $35 and #502 via 301 ht and position connects 10), sothat control poise; and 302. Placing switch 213 line 303 associated withcircuit 2 o nal 227 where the modulating signals are appiied. :neright-hand position the switch 21 -3 connects iine associated withcircuit 300 to the positive side of the DC source 2E8 to produce viarelays alterations, to be described in detaii, in the interconnectionsin circuit 300.

Line 312 from clock pulse generator 6 is now connected to counting inputline 404 of the six-stage counter (instead of being connected as i"; wasprevioasly to 322). Line'312 is also connected to line 401 which is nowisolated from 301, so that output 223 of circuit arrangement 100 cancopy, with a delay of less than half the clock pulse period, the stateof the third stage of counter 250. The outputs of ti'ielaat five stagesof counter 260 are connected by five corresponding lines to five inputsrespectively of decoder 26 whose output is connected by line 423 tocircuit 30%, in which a iink is now made between 423 and the common iine822 which ceases to be connected to 302 and circuit 303. owever, aconnec- 12 tion is made therein between 422 and those of the lines 321324which the switches 215, 216 have rendered operative; line 402isisolated from 302. i

' Terminal 223 remains connected to line 411 but the latter ceasesto beconnected in circuit 300 to line 413, and so terminal 223 is nowisolated from the converter 110. However,

" line 411 is now connected inside circuit 300 to line 414 and hgic e tothe input ofan amplifier 240 whose output is connected to a terminal 214where the frequency-shift-modulated wave modulated by the modulatingsignals applied to terminal 217 can be sampled. Output line 423 ofdecoder 264 is connected inside circuit 300 to line 412 extending to thecounting input of counter 250.

Also present between circuit 300 and decoder 264 is a line 424 (shown inFIG. 10 as a single line but in fact being a multi- -ple line) whichacts in dependence upon the positions of the switches 213216 and, moreparticularly, in dependence upon the potentials applied to 305 and 306via 215 and 216 and upon the potential of 217 applied to 303 via 213, toadjust decoder operating conditions in a manner to be describedhereinafter.

Operation is as follows:

The clock pulses of frequency F go via 312 and 404 to the counting inputof the counter and to line 401. The outputs of each of the last fivestages of counter 260 are connected to decoder 264 whose output isconnected inside circuit 300 to lines 412 and'422 via line 423, aspreviously described. The decoder, in cooperation with the counter 260,is adapted to divide the frequency F by the quotient by 16 of one orother of the factors 0,, Q for instance, 59, or 29 or 14 in the case ofQ and 57 M27 or 12 in the case of Q (assuming that the initial state forthe first two stages of counter 260 is the zero state, through theagency of appropriate control voltages derived eg from the potential of305). The required adaptation of the decoder 264 is controlled by thepotentials transmitted via 424 on the basis of the modulating signalapplied to 303 via 213 and by the potentials applied to 305 and 306 from218 via 215 and 216. The counter 250 then performs the frequencydivision by 16, the counting input of counter 250 being connected to theoutput of decoder 264 by a link between lines 412 and 423 inside circuit300.

The formation of a division factor of the kind hereinbefore referred to,for instance, the factor 57, through the agency of a decoder and binarycounter forms part of the prior art and need not be described in detailhere.

After the division by 16 a periodic signal of frequencyf or f appears atterminal 223 and goes therefrom through amplifier 240 to terminal 241 aspreviously described.

If, to simplify the demodulation-modulation changeover switchingelements, it is desired not to have to modify in such changeover theinitial states of the first two stages of the counter 260 (such statesbeing 0 and 1 respectively for bauds and 1 and 0 for 200 bauds), allthat need be done is to adjust the setting of the decoder 264 so thatcounter 260 returns to its initial state when it reaches states derivedfrom the 57 or 59, 27 or 29 or 12 or 14 states depending upon theselected transmission speed of 50 or 100 or 200 bauds, by a modificationserving to allow for the fact that the initial state chosen for one orthe other of the first two stages of the counter 260 for demodulation isthe one" state instead of the zero" state for transmission speeds of 100and 200 bauds.

The numerical values hereinbefore specified for frequencies,transmission speeds and division factors are of course purely exemplary,and the invention can, by the use of conventional calculation rules, beadapted to any other numerical values of the quantities hereinbefore setforth which are in appropriate relationships with one another. Also, ofcourse, the word relay hereinbefore employed refers preferably to anelectronic semiconductor relay which can of course be embodied atreduced cost and with reduced dimensions.

lf integrated circuit technology is used, more particularly by the useof bistable circuits of the type known as masterslave" (MS inabbreviated form), all the logic and switching circuits used in thefacility according to the invention can be devised with a specificintegrated circuit structure without de parture from the scope of theinvention.

What we claim is: 1. A demodulator device for frequency-modulatedtelegraphic signals having at least two different signal statesrepresented by a different respective predetermined nominal frequency ofa substantially sinusoidal received wave, said device comprising:

an input receiving the wave in the form of a substantially sinusoidalvoltage whose frequency may vary in time;

means for deriving from such wave, by time differentiation at selectedpassages of said voltage through zero, a control signal corresponding toeach such selected passage;

means for deriving a delayed signal from said control signal;

, a clock pulse generator delivering a sequence of clock pulses at arepetition frequency F much higher than any of said nominal frequencies;

means for applying said sequence to the counting input of a p-stagebinary counter, p denoting an integer, said counter displaying themodule 2"" residue of the number of clock pulses applied thereto;

means for controlling resetting said counter to a predetermined initialstate by said delayed signal, and

logic circuit means comprising a storage type clata-gating circuitcontrolled by said control signal and displaying the state of thecounter in the form of a group of p binary signals applied to p displayterminals respectively, said device further comprising means forcombining at least part of said group of p binary signals to form ananalog signal formed by a voltage varying in dependence upon the makeupof said group;

means for applying said analog signal to the input of a thresholdcircuit formed by cascading a low-pass filter, at least one linearamplifier and a'decision circuit having at least one threshold level,and

means for applying to a utilization terminal the signal delivered bysaid decision circuit.

2. A device as claimed in claim 1, in which said selected passagesthrough zero are the passages of said substantially sinusoidal voltagethrough zero in a predetermined direction.

3. A device as claimed in claim 2, in which said predeterminedfrequencies are two in numberand are both submultiples of said frequencyF.

' is a state other than zero for at least part of said p stages of saidcounter.

6. A device as claimed in claim 1 adapted to operate at will as ademodulator or as a modulator through the agency of selective switchingmeans providing different connections between the elements of saiddevice according to the selected operation, in which:

said binary counter comprises a first partial counter and a secondpartial counter cascaded in an order which varies according to whetherdemodulator operation or modulator operation is selected;

said device comprises means for selectively applying, according to theselected form of operation, said clock pulses to the count ng input of aselected one of said partial counters; Y

said device also comprises,-. for modulator operation, an input formodulating signals, a frequency-modulated wave output, and afrequency-dividing circuit formed by a decoder having a number of inputsconnected one each to a number of stages of said selected partialcounter and an output for the resetting thereof to said initial state,latter said output being connected to all the stages of the latterpartial counter and to the counting input of the other of said partialcounters;

said storage type gating circuit always displays the respective statesof at least part of the stages of said first and second partial countersat a corresponding number of display terminals; and saidfrequency-modulated wave output is connected to a selected one of lattersaid display terminals.

7. A device as claimed in claim 6, in which said frequencymodulated waveoutput is connected by an amplifier to latter said selected one of saiddisplay terminals.

8. A device as claimed in claim 1, in which a clipper circuit isprovided between said wave receiving input and said time difierentiationmeans.

9. A device as claimed in claim 8, [l1 WhlCh a sampling C11-

1. A demodulator device for frequency-modulated telegraphic signalshaving at least two different signal states represented by a differentrespective predetermined nominal frequency of a substantially sinusoidalreceived wave, said device comprising: an input receiving the wave inthe form of a substantially sinusoidal voltage whose frequency may varyin time; means for deriving from such wave, by time differentiation atselected passages of said voltage through zero, a control signalcorresponding to each such selected passage; means for deriving adelayed signal from said control signal; a clock pulse generatordelivEring a sequence of clock pulses at a repetition frequency F muchhigher than any of said nominal frequencies; means for applying saidsequence to the counting input of a pstage binary counter, p denoting aninteger, said counter displaying the ''''modulo 2p'''' residue of thenumber of clock pulses applied thereto; means for controlling resettingsaid counter to a predetermined initial state by said delayed signal,and logic circuit means comprising a storage type data-gating circuitcontrolled by said control signal and displaying the state of thecounter in the form of a group of p binary signals applied to p displayterminals respectively, said device further comprising means forcombining at least part of said group of p binary signals to form ananalog signal formed by a voltage varying in dependence upon the makeupof said group; means for applying said analog signal to the input of athreshold circuit formed by cascading a low-pass filter, at least onelinear amplifier and a decision circuit having at least one thresholdlevel, and means for applying to a utilization terminal the signaldelivered by said decision circuit.
 2. A device as claimed in claim 1,in which said selected passages through zero are the passages of saidsubstantially sinusoidal voltage through zero in a predetermineddirection.
 3. A device as claimed in claim 1, in which saidpredetermined frequencies are two in number and are both submultiples ofsaid frequency F.
 4. A device as claimed in claim 1, in which said partof said group of p binary signals comprises the digits of greatestweight in the binary number counted by said counter.
 5. A device asclaimed in claim 1, in which said initial state is a state other thanzero for at least part of said p stages of said counter.
 6. A device asclaimed in claim 1 adapted to operate at will as a demodulator or as amodulator through the agency of selective switching means providingdifferent connections between the elements of said device according tothe selected operation, in which: said binary counter comprises a firstpartial counter and a second partial counter cascaded in an order whichvaries according to whether demodulator operation or modulator operationis selected; said device comprises means for selectively applying,according to the selected form of operation, said clock pulses to thecounting input of a selected one of said partial counters; said devicealso comprises, for modulator operation, an input for modulatingsignals, a frequency-modulated wave output, and a frequency-dividingcircuit formed by a decoder having a number of inputs connected one eachto a number of stages of said selected partial counter and an output forthe resetting thereof to said initial state, latter said output beingconnected to all the stages of the latter partial counter and to thecounting input of the other of said partial counters; said storage typegating circuit always displays the respective states of at least part ofthe stages of said first and second partial counters at a correspondingnumber of display terminals; and said frequency-modulated wave output isconnected to a selected one of latter said display terminals.
 7. Adevice as claimed in claim 6, in which said frequency-modulated waveoutput is connected by an amplifier to latter said selected one of saiddisplay terminals.
 8. A device as claimed in claim 1, in which a clippercircuit is provided between said wave receiving input and said timedifferentiation means.
 9. A device as claimed in claim 8, in which asampling circuit controlled by said clock pulse generator is introducedbetween said clipper circuit and time differentiation means.